1. Technical Field
This invention relates to memory devices and more specifically to a sense amplifier providing a high speed sensing with high speed read operations in static random access memory (SRAM) circuits.
2. Description of Related Art
In an integrated memory circuit, a sense amplifier is used to improve the speed of a memory and to provide signals, which conform to the requirements of driving peripheral circuits within the memory. Due to large arrays of SRAM cells, a resulting signal of a read operation has a low voltage swing (on the order of few tens of millivolts). The sense amplifier is used to sense this small swing and provide the corresponding full rail-to-rail voltages. The sense amplifier senses the difference between a true bit line and a complimentary bit line during a read operation and amplifies the difference, so that the resulting signal will have a swing width from a ground voltage to a supply voltage.
FIG. 1 illustrates a general configuration for an SRAM column. The SRAM column includes ‘N’ number of rows in one column. During a read cycle, one of the N word lines goes high and a corresponding memory cell discharges a bit line (if logic ‘0’ is stored in the memory cell) or a complementary bit line (if logic ‘1’ is stored in the memory cell). When a sufficient voltage difference is created between the true bit line and the complementary bit line, the sense amplifier is enabled, the voltage difference is amplified and an output data is generated corresponding to a data stored in the memory cell.
FIG. 2 illustrates a circuit diagram 200 for a conventional cross-coupled latch type sense amplifier. It consists of two PMOS transistors MP1 and MP2 and two NMOS transistors MN1 and MN2 connected between a true bit line and a complementary bit line BITIO and BITBIO. The transistors MP1 and MN1 and the transistors MP2 and MN2 are individually connected to form two invertors. The two invertors are cross coupled to form a latch circuit. The sense amplifier also consists of two PMOS transistors MP3 and MP4, with one terminal connected to the bit line, the other terminal connected to the latch output node. A gate terminal of each transistor receives a control signal SAEN1. The transistors MP3 and MP4 transfer a resulting signal of a read operation from the bit lines to the cross coupled latch nodes INP and INN in response to the control signal SAEN1. The NMOS transistor MN3 is configured to provide a ground voltage to the cross coupled latch in response to the control signal SAEN1, with its drain connected to the latch and its source connected to ground (GND). The gate terminal of the MN3 also receives the control signal SAEN1.
The true and complimentary bit lines BITIO and BITBIO are supplied with a true and a complementary data signals from the memory cells. The control signal SAEN1 is kept at a logic low causing the PMOS transistors MP3 and MP4 to conduct and thereby passing on the swing generated by the memory cell to the latch. The SAEN1 control signal is then transitioned to logic high, causing a supply voltage VDD and the ground GND to be connected to the latch. One of the voltages transferred from the bit lines and having a higher value would cause one of the NMOS transistors MN1 or MN2 to conduct more than the other. The transistor that conducts less (MN1 or MN2) will have a lesser voltage at the drain terminal in comparison to the other NMOS transistor in the latch circuit. As a result, one of transistor MP1 or MP2 will conduct. Decreasing the rate of fall of the slower transistor further eventually brings it into a cut off state. The PMOS itself will move into a saturation region of operation. Then, the junction nodes of INP and INN will be placed at two extremes of the supply voltage, i.e., one is pulled up to the supply voltage VDD and the other is pulled down to the ground voltage GND, depending on the value of the data signals received from the memory cells. This value is fed to an inverter, which further amplifies the signal and provides the output. Thus, the cross coupled latch sense amplifier amplifies the true and the complementary data signals by a difference (VDD-GND), where VDD is a supply voltage and GND is a ground voltage.
However, the cross coupled latch sense amplifier imposes a very high capacitance on the bit lines and thereby slows down the discharge rate. Therefore, the read operation will be slower. To overcome this problem, alpha-latch type sense-amplifier have been proposed.
FIG. 3 illustrates a circuit diagram 300 of a conventional alpha type latch sense amplifier. The amplifier consists of two PMOS transistors MP1 and MP2 and two NMOS transistors MN1 and MN2 connected between true and complementary bit lines BITIO and BITBIO. The transistors MP1 and MN1 and the transistors MP2 and MN2 are individually connected to form two invertors. The two invertors are cross coupled so as to form a latch. Two NMOS transistors MN3 and MN4 have their drains connected to sources of the NMOS transistors MN1 and MN2, and their sources connected to the drain of an NMOS transistor MN5. The gates of MN3 and MN4 are connected to the bit lines BITIO and BITBIO. The transistor MN5 has its drain connected to the transistors MN3 and MN4, its source connected to a ground (GND) and its gate configured to receive a control signal SAEN1.
The operation of the alpha latch type sense amplifier is similar to that of the cross coupled latch sense amplifier. One difference is that the true and complementary data signals from the memory cells are fed to the sense amplifier circuit through the gates of the transistors MN3 and MN4. The control signal SAEN1 is kept at a high logic for causing the transistors MN5, MN3 and MN4 to conduct and thereby passing on the swing generated by the memory cell on the bit lines to the latch and causing a supply voltage VDD and a ground GND voltage to be connected to the latch. The cross coupled latch starts functioning and nodes INP and INN are driven to the supply voltage and the ground voltage, depending on the true and complimentary data signals transferred from the memory cells.
Due to an alpha type connection in the alpha latch type sense amplifiers, the input capacitance imposed on the bit lines is less than with the cross coupled latch sense amplifier of FIG. 2. However, the resolution time is poor with this alpha type because of the stack of three transistors as compared to a stack of two transistors in the cross coupled latch type sense amplifier.
It will be noted that the prior art discussed above does not overcome certain major prevailing problems such as: slower read operations, poor resolving time, etc.
Therefore, there is a need for a sense amplifier to provide a high speed read operation with a faster sensing speed for use in SRAM circuits. Moreover, the sense amplifier should provide for a low resolution time.